1. Field of the Invention
The present invention generally relates to data processing systems and communication systems. More particularly, the invention relates to methods and apparatus for encoding predicted values into an instruction stream without the need for additional bits or areas of a device such a cache.
2. Description of the Related Art
Users of data processing systems continue to demand greater performance for handling increasingly complex and difficult tasks. Greater performance from the processors that operate such systems may be obtained through faster clock speeds so the individual instructions are processed more quickly. However, processing speed has increased much more quickly than the speed of main memory. Despite the speed of a processor, a bottleneck on computer performance is that of transferring information between the processor and memory. Therefore, cache memories, or caches, are often used in many data processing systems to increase performance in a relatively cost-effective manner.
A cache is typically a relatively faster memory that is intermediately coupled between one or more processors and a bank of slower main memory. Cache speeds processing by maintaining a copy of repetitively used information in its faster memory. Whenever an access request is received for information not stored in cache, the cache typically retrieves the information from main memory and forwards the information to the processor. If the cache is full, typically the least recently used information is discarded or returned to main memory to make room for more recently accessed information.
The benefits of a cache are realized whenever the number of requests to address locations of cached information (known as “cache hits”) are maximized relative to the number of requests to memory locations containing non-cached information (known as “cache misses”). Despite the added overhead that occurs as a result of a cache miss, as long as the percentage of cache hits is high (known as the “hit rate”), the overall processing speed of the system is increased.
Illustratively, one method of increasing the hit rate for a cache is to increase the size of the cache. However, cache memory is relatively expensive and is limited by design constraints, particularly if the cache is integrated with a processor on the same physical integrated circuit. This is especially true if a method or scheme require extra area or space of a cache memory such as an instruction cache RAM of an instruction cache subsystem.
As an illustration, one cost-effective alternative is to chain together multiple caches of varying speeds. A smaller but faster primary cache is chained to a relatively larger but slower secondary cache. Furthermore, instructions and data may be separated into separate data and instruction caches. Illustratively, some processors implement a small internal level one (L1) instruction cache with an additional external level two (L2) cache, and so on.
Furthermore, it is known to have two separate caches within a computer system, i.e., an instruction cache, also know as an I-cache; and a data cache, also known as D-cache. The I-cache is used for storing instructions.
One application of the I-cache is the use of value prediction based on re-usage of a previous code execution result derived from a stable history value. This application requires stable history values for executions through dependencies and the dependency that limits performance for integer code, netting a substantial performance gain. However, most modern computer architectures are 64-bit architectures. For a cache to retain enough 64-bit values to maintain an acceptable hit rate requires quite a large storage area within the cache. Furthermore, in addition to taking significant chip area or storage area, an additional array of the same size (64-bit) will slow down operational speed, which necessarily limits performance gain.
Therefore, there is need for a method and apparatus for storing additional information (such as predicted values) in an instruction stream without requiring additional space.